1. Field of the Invention
The invention relates in general to a multi-chip package, and more particularly to a multi-chip package using conductive layer as a transfer terminal for wires.
2. Description of the Related Art
The increase in the demand for high density and high efficiency and the cost/benefit concern are a great impetus to the research and development as well as the application of the multi-chip package (MCP). The package module integrates the system with many chips, and can select one or more than one passive element. However, the problem is that when more chips and passive elements are integrated together, the wire bonding becomes more difficult.
For example, under the structure of a quad flat package (QFP), carrying two chips would be enough to cause difficulty in wire bonding. Referring to FIG. 1, a top view and a side view of conventional quad flat package (QFP) are shown. The die pad 10 of the lead frame carries a bottom die 20 and top die 30. The bottom die 20 is electrically connected to the die pad 10 through the first wire L1. The top die 30 is electrically connected to the first chip 20 through the third wire L3 and is connected to the die pad 10 and through the second wire L2. Beside, the die pad 10, the bottom die 20 and the top die 30 are electrically connected to the lead 40 through the fourth wire L4, the fifth wire L5 and the sixth wire L6 respectively.
However, the third wire is easily entangled with neighboring wires or other wire groups, hence incurring short-circuiting. As the layout of wiring is too intensified and against wiring principles, diligence is required when bonding the third wire lest neighboring wires might be damaged or indented. Despite no damage or indent occurs during wire bonding, the problem of wire sweeping is very likely to occur during the subsequent process of sealing the package with a liquid sealant. Wire sweeping leads to short-circuiting and affects the yield rate severely. Besides, if the position of the die is shifted such that one wire contact with each other, the likelihood of short-circuiting is still reduced. The above factors affect the yield rate to a great extent. Therefore, how to work out an efficient solution capable of resolving the wire bonding problem occurring when many chips are passive elements are integrated in the same package has become an imminent issue to be resolved in the industry of multi-chip package.